The serial data output pin (SDO) serves two purposes. It can be
used to read the contents of the wiper setting and EEMEM values
using Instruction 10 and Instruction 9, respectively. The remaining
instructions (Instruction 0 to Instruction 8, Instruction 11 to
Instruction 15) are valid for daisy-chaining multiple devices in
simultaneous operations. Daisy-chaining minimizes the number
of port pins required from the controlling IC (see Figure 41). The
SDO pin contains an open-drain N-Ch FET that requires a pull-up
resistor, if this function is used. As shown in Figure 41, users need
to tie the SDO pin of one package to the SDI pin of the next package.
Users may need to increase the clock period because the pull-up
resistor and the capacitive loading at the SDO-to-SDI interface may
require additional time delay between subsequent devices.
When two AD5235s are daisy-chained, 48 bits of data are
required. The first 24 bits (formatted 4-bit command, 4-bit
address, and 16-bit data) go to U2, and the second 24 bits with
the same format go to U1. Keep CS low until all 48 bits are
clocked into their respective serial registers. CS is then pulled
high to complete the operation.
SDI U1 SDO
SDI U2 SDO
Figure 41. Daisy-Chain Configuration Using SDO
TERMINAL VOLTAGE OPERATING RANGE
The positive VDD and negative VSS power supplies of the AD5235
define the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on Terminal A,
Terminal B, and Terminal W that exceed VDD or VSS are clamped by
the internal forward-biased diodes (see Figure 42).
Figure 42. Maximum Terminal Voltages Set by VDD and VSS
The GND pin of the AD5235 is primarily used as a digital
ground reference. To minimize the digital ground bounce,
the AD5235 ground terminal should be joined remotely to
the common ground (see Figure 43). The digital input control
signals to the AD5235 must be referenced to the device ground
pin (GND) and must satisfy the logic level defined in the
Specifications section. An internal level-shift circuit ensures
that the common-mode voltage range of the three terminals
extends from VSS to VDD, regardless of the digital input level.
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 42), it
is important to power VDD and VSS first before applying any
voltage to Terminal A, Terminal B, and Terminal W. Otherwise,
the diode is forward-biased such that VDD and VSS are powered
unintentionally. For example, applying 5 V across Terminal A
and Terminal B prior to VDD causes the VDD terminal to exhibit
4.3 V. It is not destructive to the device, but it might affect the
rest of the user’s system. The ideal power-up sequence is GND,
VDD and VSS, digital inputs, and VA, VB, and VW. The order of
powering VA, VB, VW, and the digital inputs is not important as
long as they are powered after VDD and VSS.
Regardless of the power-up sequence and the ramp rates of the
power supplies, when VDD and VSS are powered, the power-on
preset activates, which restores the EEMEM values to the RDAC
Layout and Power Supply Bypassing
It is a good practice to employ compact, minimum lead-length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Bypass supply leads to
the device with 0.01 μF to 0.1 μF disk or chip ceramic capacitors.
Also, apply low ESR, 1 μF to 10 μF tantalum or electrolytic
capacitors at the supplies to minimize any transient disturbance
(see Figure 43).
Figure 43. Power Supply Bypassing
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