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AD362SD/883B View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
AD362SD/883B Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
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Interfacing to Popular Analog to Digital Converters
Figure 7a shows the AD362 driving an AD ADC80. The
The AD362 has been designed to interface directly to most
AD ADC80 is a 12-bit, 25-microsecond, low-cost ADC that
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analog to digital converters; often no additional components
meets all of the requirements listed above. Throughput rate
are required and only two interconnections must be made.
is typically 30kHz with no missing codes over the operating
The direct interface requirements for the ADC are as follows:
temperatUre range.
1. The ADC StatUs output must be positive-true Logic ("1"
during conversion).
2. Transition from "0" to "1" must occur at least 200ns
Figure 7b shows a lO-bit application based on the AD362 and
the AD571, a complete low cost 10-bit, 25-microsecond ADC.
In this case, two of the above requirements are not met:
before the most significant bit decision is made (successive
approximation ADC) or before input integration starts
(integrating type ADC).
3. StatUs must not retUrn to "0" before the LSB decision is
made (see page 5).
1. DR (DATA READY), as StatUs, is positive-true but. . .
2. DR does not indicate that a conversion is in progress until
1.5JJs after conversion starts.
3. DR does indicate conversion complete after the LSB deci-
sion is made, but. . .
-
OBSOLETE 4. If StatUs isbeing used to latch output data, it must not
retUrn to Logic "0" until all output data bits are valid and
available.
Complete system throughput performance is determined by
combining the worst-case specifications of the AD362 and the
ADC. If guaranteed system performance is required, the
AD363 and AD364 are recommended. The AD363 includes
an AD362 and an AD572 12-bit, 25-microsecond precision
ADC. The AD364 consists of an AD362 and an AD574 12-bit,
microprocessor-compatible, low cost ADC. Each is specified
as a complete, two-package system; data sheets are available
upon request.
4. DR precedes the enabling of the AD571 output 3-state
gates by 500ns.
The gating provided by Ul allows the applied convert com--
mand (CC) to initiate input hold at the AD362. CC must last
for more than 1.5JJs so that DR may then assume control
of Hold. If conversion is continuous (consistent with multi-
channel operation), the next convert command can be used to
load the previously-converted data into an output register. For
single conversion operation, a IJJs delay of the falling edge of
DR may be used to signify valid data.
DC POWER
DC POWER
DATA
BITS
OUT
ANALOG
(101
INPUTS
AO571
(IS)
ANALOG
INPUTS
1161
AOJ62
CAPACITOR
0
IANALOGHOALNDALOGI ADAOC80
OUT
IN
BITS
OUT
D(A1T2A)
SAMPLE/HOLD I
I STATUSOUTPUT
CHANNEL
SELECT
LATCH
DR
Me'
CHANNEl
SELECT
LATCH
.n. DATA STROBE
CONVERT ITO OUTPUT
START
REGISTERI
CONVERT
COMMAND
~1.5~.
--::J C MIN
1/474LSJ2
DATA STROBE
(TO OUTPUT
REGISTER)
a. l2-Bit DAS Using AD362 and AD ADC80
b. la-Bit DAS UsingAD362 and AD571
Figure 7. Data Acquisition Systems Based on the AD362 and Popular ADC's
I
-7-
 

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