AD362 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD362 Datasheet PDF : 8 Pages
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The normal sequence of events is as follows:
1. The appropriate Channel Select Address is latched into the
address register. Time is allowed for the multiplexers to
2. Trigger the oscilloscope on Status. Delay the display such
that Status is mid-screen.
3. Observe the LSB data output of the ADC.
settle.
4. Vary the analog input control to confirm that the LSB
2. A Convert Start command is issued to the ADC which, in
transition precedes the Status transition.
response, indicates that it is "busy" by placing a Logic "1"
on its Status line.
3. The ADC Status controls the sample-and-hold. When the
ADC is"busy", the sample-and-hold is in the Hold mode.
Sin~le-Ended/Differential Mode Control
The AD362 features an internal analog switch that configures
the Analog Input Section in either a 16-channel single-ended
or 8-channel differential mode. This switch is controlled by a
4. The ADC goes into its conversion routine. Since the sample- TTL logic input applied to pin 1 of the Analog Input Section:
and-hold is holding the proper analog value, the address
may be updated during conversion. Thus multiplexer set-
"0": Single-Ended (16 channels)
"1 ": Differential (8 channels)
tling time can coincide with conversion and need not affect
throughput rate.
When in the differential mode, a differential source may be
I
5. The ADC indicates completion of its conversion by return-
ing Status to Logic "0". The sample-and-hold returns to
the Sample mode.
6. If the input signal has changed full-scale (different channels
may have widely-varying data) the sample-and-hold will
Otypically require 10 microseconds to "acquire" the next
input to sufficient accuracy for 12-bit conversion.
B Mter allowing a suitable interval for the sample-and-hold to
S stabilize at its new value, another Convert Start command may
be issued to the ADC.
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applied between corresponding "High" and "Low" analog
input channels.
It is possible to mix SE and DIFF inputs by using the mode
control to command the appropriate mode. In this case, four
microseconds must be allowed for the output of the Analog
Input Section to settle to within :to.OI % of its final value, but
if the mode is switched concurrent with changing the channel
address, no significant additional delay is introduced. The
effect of this delay may be eliminated by changing modes
while a conversion is in progress (with the sample-and-hold
in the "Hold" mode). When SE and DIFF signals are being
processed concurrently, the DIFF signals must be applied
between corresponding "High" and "Low" analog input chan-
nels. Another application of this feature is the capability of
measuring 16 sources individually andlor measuring differences
between pairs of those sources.
UNDER TEST
-15V
Input Channel Addressin~
Table 1 is the truth table for input channel addressing in both
STATUS
the single-ended and differential modes. The 16 single-ended
channels may be addressed by applying the corresponding
CHANNEL A "1"~
"STATUS" "o"_'_~
I
I
CHANNEL B
"LSB"
'II
--.
I,
: VALIDDATA
I
.--STATUSDELAY
digital number to the four Input Chanl1el Select address bits,
AE, AD, AI, A2 (pins 28-31). In the differential mode, the
eight channels are addressed by applying the appropriate
digital code to AD, Al and A2; AE must be enabled with a
NOTE:
Figure4. ADC Status Valid Test
Logic "1 ". Internal logic monitors the status of the SE/DIFF
Mode input and addresses the multiplexers singularly or in
pairs as required.
Valid OutPut Data
Not all ADCs have all data bits available when Status indicates
ADDRESS
ON-C-H--A-N-N--E-L- (Pin Number)
that the conversion is complete. Successive approximation
ADCs based on the 250213/4 type of register must have a Status
delay built in or the final data bit will lag Status by approx-
imately SOns. This will result in two problems:
1. The sample-and-hold will return to Sample, disturbing the
analog input to the ADC as it is attempting to convert the
least significant bit. This may result in an error.
2. If the falling edge of Status is being used to load the data
into a register, the least significant bit will not be valid
.
when loaded.
An external lOOns delay or use of an ADC with a valid Status
output is necessary to prevent this problem. The applications
shown in this data sheet ensure that all data bits will be valid.
The following test may be made to determine if the ADC
Status timing is correct:
1. Connect the ADC under test as shown in Figure 4.
AE A2 A1 AO
00 00
0001
0 0 10
00 11
0 100
0 101
0 1 10
0 111
10 00
1001
10 10
10 11
1 100
110 1
1 1 10
1 --...-1 1 !
~
Ended
0 (11)
1 (10)
2m
3 (8)
4 (7)
5 (6)
6 (5)
7 (4)
8 (27)
9 (26)
10 (25)
11 (24)
12 (23)
13 (22)
14 (19)
~-Q~l
Differential
"Hi"
"La"
None
None
~~
None
None
None
None
None
0 (11) 0 (27)
1 (10) 1 (26)
2 (9) 2 (25)
3 (8)
4 (7)
3 (24)
5 (23)
5 (6)
6 (5)
5 (22)
6 (19)
7 ~4)_- 7 (18)
Table 1. Input Channel Addressing Truth Table
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