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AD2S80ATD View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
AD2S80ATD Datasheet PDF : 16 Pages
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AD2S80A
DATA TRANSFER
To transfer data the INHIBIT input should be used. The data
will be valid 600 ns after the application of a logic LOto the
INHIBIT. This is regardless of the time when the INHIBIT is
applied and allows time for an active BUSY to clear. By using
the ENABLE input the two bytes of data can be transferred
after which the INHIBIT should be returned to a logic HI
state to enable the output latches to be updated.
BUSY Output
The validity of the output data is indicated by the state of the
BUSY output. When the input to the converter is changing, the
signal appearing on the BUSY output is a series of pulses at
TTL level. A BUSY pulse is initiated each time the input moves
by the analog equivalent of one LSB and the internal counter is
incremented or decremented.
INHIBIT Input
The INHIBIT logic input only inhibits the data transfer from
the up-down counter to the output latches and, therefore, does
not interrupt the operation of the tracking loop. Releasing the
INHIBIT automatically generates a BUSY pulse to refresh the
output data.
ENABLE Input
The ENABLE input determines the state of the output data. A
logic HImaintains the output data pins in the high imped-
ance condition, and the application of a logic LOpresents the
data in the latches to the output pins. The operation of the
ENABLE has no effect on the conversion process.
BYTE SELECT Input
The BYTE SELECT input selects the byte of the position data
to be presented at the data output DB1 to DB8. The least signifi-
cant byte will be presented on data output DB9 to DB16 (with
the ENABLE input taken to a logic LO) regardless of the
state of the BYTE SELECT pin. Note that when the AD2S80A is
used with a resolution less than 16 bits the unused data lines are
pulled to a logic LO.A logic HIon the BYTE SELECT input
will present the eight most significant data bits on data output
DB1 and DB8. A logic LOwill present the least significant
byte on data outputs 1 to 8, i.e., data outputs 1 to 8 will dupli-
cate data outputs 9 to 16.
The operation of the BYTE SELECT has no effect on the con-
version process of the converter.
RIPPLE CLOCK
As the output of the converter passes through the major carry,
i.e., all 1sto all 0sor the converse, a positive going edge on
the RIPPLE CLOCK (RC) output is initiated indicating that a
revolution, or a pitch, of the input has been completed.
The minimum pulse width of the ripple clock is 300 ns. RIPPLE
CLOCK is normally set high before a BUSY pulse and resets
before the next positive going edge of the next consecutive pulse.
The only exception to this is when DIR changes while the
RIPPLE CLOCK is high. Resetting of the RIPPLE clock will
only occur if the DIR remains stable for two consecutive posi-
tive BUSY pulse edges.
If the AD2S80A is being used in a pitch and revolution count-
ing application, the ripple and busy will need to be gated to
prevent false decrement or increment (see Figure 2).
RIPPLE CLOCK is unaffected by INHIBIT.
5V
RIPPLE
CLOCK
BUSY
IN4148
5V
5k
IN4148
10k1k
2N3904
0V
TO COUNTER
(CLOCK)
NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS "LO."
Figure 2. Diode Transistor Logic Nand Gate
DIRECTION Output
The DIRECTION (DIR) logic output indicates the direction of
the input rotation. Any change in the state of DIR precedes the
corresponding BUSY, DATA and RIPPLE CLOCK updates.
DIR can be considered as an asynchronous output and can
make multiple changes in state between two consecutive LSB
update cycles. This corresponds to a change in input rotation
direction but less than 1 LSB.
DIGITAL TIMING
BUSY
VH
t1
RIPPLE
CLOCK
t2 VH
VL
t4 VH
t3
DATA
INHIBIT VH
t6
t5
VL
VH
t7
DIR
VL
INHIBIT
t8
VL
t9
ENABLE
VL
t 10
VZ
DATA
BYTE
SELECT
t 11
VL
DATA
t 12
VH
VL
VH
VH
t 13
VL
PARAMETER
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
TMIN
TMAX
CONDITION
200
600
BUSY WIDTH VH–VH
10
25
RIPPLE CLOCK VH TO BUSY VH
470
580
RIPPLE CLOCK VL TO NEXT BUSY VH
16
45
BUSY VH TO DATA VH
3
25
BUSY VH TO DATA VL
70
140
INHIBIT VH TO BUSY VH
485
625
MIN DIR VH TO BUSY VH
515
670
600
40
110
35
110
MIN DIR VH TO BUSY VH
INHIBIT VL TO DATA STABLE
ENABLE VL TO DATA VH
ENABLE VL TO DATA VL
60
140
BYTE SELECT VL TO DATA STABLE
60
125
BYTE SELECT VH TO DATA STABLE
REV. B
–9–
 

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