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AD2S80ATD/883B View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
AD2S80ATD/883B Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Parameter
Conditions
Min
Typ
Max
DATA LOAD
Sense
Internally Pulled High (100 k)
to VS. Logic LO Allows
Data to be Loaded into the
Counters from the Data Lines
150
300
BUSY3
Sense
Width
Load
Logic HI When Position O/P
Changing
200
600
Use Additional Pull-Up
1
DIRECTION3
Sense
Logic HI Counting Up
Logic LO Counting Down
Max Load
3
RIPPLE CLOCK3
Sense
Width
Reset
Load
Logic HI
All 1s to All 0s
All 0s to All 1s
Dependent on Input Velocity
300
Before Next Busy
3
DIGITAL INPUTS
High Voltage, VIH
Low Voltage, VIL
DIGITAL INPUTS
High Current, IIH
Low Current, IIL
DIGITAL INPUTS
Low Voltage, VIL
Low Current, IIL
DIGITAL OUTPUTS
High Voltage, VOH
Low Voltage, VOL
THREE-STATE LEAKAGE
Current IL
INHIBIT, ENABLE
2.0
DB1–DB16, Byte Select
± VS = ± 10.8 V, VL = 5.0 V
INHIBIT, ENABLE
DB1–DB16, Byte Select
± VS = ± 13.2 V, VL = 5.0 V
INHIBIT, ENABLE
DB1–DB16
± VS = ± 13.2 V , VL = 5.5 V
INHIBIT, ENABLE
DB1–DB16, Byte Select
± VS = ± 13.2 V, VL = 5.5 V
ENABLE = HI
SC1, SC2, Data Load
± VS = ± 12.0 V, VL = 5.0 V
ENABLE = HI
SC1, SC2, Data Load
± VS = ± 12.0 V, VL = 5.0 V
DB1–DB16
2.4
RIPPLE CLK, DIR
± VS = ± 12.0 V, VL = 4.5 V
IOH = 100 µA
DB1–DB16
RIPPLE CLK, DIR
± VS = ± 12.0 V, VL = 5.5 V
IOL = 1.2 mA
DB1–DB16 Only
± VS = ± 12.0 V, VL = 5.5 V
VOL = 0 V
± VS = ± 12.0 V, VL = 5.5 V
VOH = 5.0 V
0.8
؎100
؎100
1.0
–400
0.4
± 100
± 100
NOTES
1Refer to small signal bandwidth.
2Output offset dependent on value for R6.
3Refer to timing diagram.
Specifications subject to change without notice.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.
AD2S80A
Unit
ns
ns
LSTTL
LSTTL
LSTTL
V
V
µA
µA
V
µA
V
V
µA
µA
REV. B
–3–
 

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