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AD1385KD Просмотр технического описания (PDF) - Analog Devices

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AD1385KD 16-Bit 500 kHz Wide Temperature Range Sampling ADC ADI
Analog Devices ADI
AD1385KD Datasheet PDF : 20 Pages
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mode as long either Hold Command Out or Start Convert is
high. Care is needed in defining system timing to ensure that
the T/H has a minimum of 700 ns for signal acquisition before
another conversion begins. The minimum width of Start Con-
vert is 20 ns, the sum of tSCS and tSCH, the minimum setup and
hold times.
Transmission line effects at the Start Convert and Hold Com-
mand In inputs should be considered when designing circuit
boards for the AD1385. A series termination resistor of 50 to
100 is recommended when the source of either of these sig-
nals is more than a few inches away from the AD1385. This will
control reflections and transients which could otherwise degrade
the part’s performance.
Output Data
The output data are multiplexed in two bytes onto an 8-bit data
bus. Data are guaranteed to be stable at the time of the edges of
Data Strobe (Pin 15). Hi/Lo Byte Select (Pin 16) controls
which byte is presented first. If Hi/Lo Byte Select is high, then
BYTE0 is B9–B16 and BYTE1 is B1–B8. The order of the data
bytes is interchanged when Hi/Lo Byte Select is low. BYTE 0
and BYTE 1 are defined in the timing diagram Figure 17. B1 is
the most significant bit of the reconstructed 16-bit data.
B1 SELECT (Pin 44) determines whether data is presented in
complementary twos complement or complementary offset bi-
nary form. Complementary twos complement data is provided
when B1 Select is LOW. OE may be used to place the data bus
into a high impedance state.
The arithmetic unit in the AD1385 saturates at all 0s or all 1s if
the input range is exceeded.
Figure 20. Full-Scale Power Spectral Density after Power-
up at TCASE = +25°C Without Calibration, ±5 V Range,
16384-Point FFT, 500 kHz Sample Rate. Compare with
Figure 4.
Table I.
B1 Select
Data Format
–Full-Scale Data
0 V Data
+Full-Scale Data
Complementary Twos Complementary Offset
Figure 21. Full-Scale Power Spectral Density at TCASE =
+125°C, Calibration Performed at TCASE = +25°C, ±5 V
Range, 16384-Point FFT, 500 kHz Sample Rate
CALIBRATION (Pins 28 and 41)
Calibration corrects for linearity errors in the Reference DAC
arising from internal component mismatches or temperature
changes. It has a negligible effect on gain and offset errors, and
these should be corrected by other means. The AD1385 must
be calibrated after power-up, and recalibration is recommended
whenever the part’s temperature has changed by more than
15°C. Performance degrades gracefully with temperature
changes, resulting in small but gradual decreases in SNR and
increases in distortion which may be eliminated by recalibra-
tion. Calibration codes are stored in internal RAM and are lost
when power is removed. Figures 20–22 show the effects of
uncalibrated versus calibrated operation.
Figure 22. Same as Figure 21 Following Recalibration at
TCASE = +125°C
REV. 0
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