Dead Time and Propagation Delay Specifications
The ACPL-P341/W341 includes a Propagation Delay Dif-
ference (PDD) specification intended to help designers
minimize“dead time”in their power inverter designs. Dead
time is the time period during which both the high and
low side power transistors (Q1 and Q2 in Figure 22) are off.
Any overlap in Q1 and Q2 conduction will result in large
currents flowing through the power devices between the
high and low voltage motor rails.
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn off of LED1)
so that under worst-case conditions, transistor Q1 has
just turned off when transistor Q2 turns on, as shown in
Figure 27. The amount of delay necessary to achieve this
condition is equal to the maximum value of the propa-
gation delay difference specification, PDDMAX, which is
specified to be 100 ns over the operating temperature
range of 40° C to 105° C.
Delaying the LED signal by the maximum propagation
delay difference ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time is equivalent
to the difference between the maximum and minimum
propagation delay difference specifications as shown in
Figure 28. The maximum dead time for the ACPL-P341/
W341 is 200 ns (= 100 ns - (-100 ns)) over an operating
temperature range of -40° C to 105° C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other and
are switching identical IGBTs.
Figure 27. Minimum LED skew for zero dead time
Figure 28. Waveforms for dead time