Figure 23 shows a typical gate driver’s high current output
stage with 3 bipolar transistors in darlington configuration.
During the output high transition, the output voltage rises
rapidly to within 3 diode drops of VCC. To ensure the VOUT
is at VCC in order to achieve IGBT rated VCE(ON) voltage. The
level of VCC will be need to be raised to beyond VCC+3(VBE)
to account for the diode drops. And to limit the output
voltage to VCC, a pull-down resistor, RPULL-DOWN between
the output and VEE is recommended to sink a static current
while the output is high.
ACPL-P341 uses a power PMOS to deliver the large current
and pull it to VCC to achieve rail-to-rail output voltage
as shown in Figure 24. This ensures that the IGBT’s gate
voltage is driven to the optimum intended level with no
power loss across IGBT even when an unstable power
supply is used.
Figure 23. Typical gate driver with output stage in darlington configuration
Figure 24. ACPL-P341/W341 with PMOS and NMOS output stage for rail-to-rail output voltage