GS88118BD-133 View Datasheet(PDF) - Giga Semiconductor

Part Name

Description

Manufacturer

GS88118BD-133

512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

Giga Semiconductor 

GS88118B(T/D)/GS88132B(D)/GS88136B(T/D)

Simplified State Diagram with G

X

Deselect

W

R

W

R

X

First Write R

CW

CR

W

First Read X

CW

CR

W

X

R

Burst Write

CR

CW

R

W

Burst Read X

CW

CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles.

3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

Rev: 1.00b 12/2002

14/34

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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