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GS88118BT-225I View Datasheet(PDF) - Giga Semiconductor

Part NameGS88118BT-225I GSI
Giga Semiconductor GSI
Description512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88118BT-225I Datasheet PDF : 34 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
GS88118B(T/D)/GS88132B(D)/GS88136B(T/D)
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
L
LBO
H
Linear Burst
Interleaved Burst
Output Register Control
L
FT
H or NC
Flow Through
Pipeline
Power Down Control
L or NC
ZZ
H
Active
Standby, IDD = ISB
Note:
There arepull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.00b 12/2002
10/34
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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