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GS881Z36BT-200 View Datasheet(PDF) - Giga Semiconductor

Part NameGS881Z36BT-200 GSI
Giga Semiconductor GSI
Description9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS881Z36BT-200 Datasheet PDF : 39 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
GS81Z18/32/36D 165-Bump BGA Pin Description
Symbol
A0, A1
A
DQA
DQB
DQC
DQD
BA, BB, BC, BD
NC
CK
CKE
W
E1
E3
E2
G
ADV
ZZ
FT
LBO
TMS
TDI
TDO
TCK
MCH
DNU
VDD
VSS
VDDQ
Type
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
Data Input and Output pins
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
No Connect
Clock Input Signal; active high
Clock Enable; active low
Write Enable; active low
Chip Enable; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active high
Sleep mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Must Connect High
Do Not Use
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.04 10/2004
9/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology
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Functional Description
The GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D) is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard packages
• Pb-Free 100-lead TQFP package available

 

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