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GS881Z36BT-150I View Datasheet(PDF) - Giga Semiconductor

Part NameGS881Z36BT-150I GSI
Giga Semiconductor GSI
Description9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS881Z36BT-150I Datasheet PDF : 39 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
BB
NC
E3 CKE ADV A17
A
A
A
B
NC
A
E2
NC BA CK
W
G
A
NC
B
C
NC
NC VDDQ VSS
VSS
VSS
VSS
VSS VDDQ NC
DQA
C
D
NC
DQB VDDQ VDD
VSS
VSS
VSS
VDD VDDQ NC
DQA
D
E
NC
DQB VDDQ VDD
VSS
VSS
VSS
VDD VDDQ NC
DQA
E
F
NC
DQB VDDQ VDD
VSS
VSS
VSS
VDD VDDQ NC
DQA
F
G
NC
DQB VDDQ VDD
VSS
VSS
VSS
VDD VDDQ NC
DQA
G
H
FT
MCH NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
H
J
DQB
NC VDDQ VDD
VSS
VSS
VSS
VDD VDDQ DQA
NC
J
K
DQB
NC VDDQ VDD
VSS
VSS
VSS
VDD VDDQ DQA
NC
K
L
DQB
NC VDDQ VDD
VSS
VSS
VSS
VDD VDDQ DQA
NC
L
M
DQB
NC VDDQ VDD
VSS
VSS
VSS
VDD VDDQ DQA
NC
M
N
DQB NC VDDQ VSS
NC
NC
NC
VSS VDDQ NC
NC
N
P
NC NC
A
A
TDI A1 TDO A
A
A
NC
P
R
LBO NC
A
A TMS A0 TCK A
A
A
A
R
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.04 10/2004
6/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology
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Functional Description
The GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D) is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard packages
• Pb-Free 100-lead TQFP package available

 

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