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GS881Z32BT-300 View Datasheet(PDF) - Giga Semiconductor

Part NameGS881Z32BT-300 GSI
Giga Semiconductor GSI
Description9Mb Pipelined and Flow Through Synchronous NBT SRAM


GS881Z32BT-300 Datasheet PDF : 39 Pages
First Prev 31 32 33 34 35 36 37 38 39
GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)
9Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
881Z18B_r1
881Z18B_r1;
881Z18B_r1_01
881Z18B_r1_01;
881Z18B_r1_02
881Z18B_r1_02;
881Z18B_r1_03
881Z18B_r1_03;
881Z18B_r1_04
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
Content
• Added x32 TQFP
• Removed address and DQ number designations
Content/Format
Content/Format
Content
• Updated Current Numbers
• Basic page 1 format updates
• Updated Synchronous Truth Table
• Updated Package Thermal Table
• Removed erroneous speed bins
• Added 333/300 MHz speed bins
• Corrected 165 BGA mechanical drawing
• Format updates
• Added Pb-free information to TQFP
• Added variation information to 165 BGA
Rev: 1.04 10/2004
39/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology
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Functional Description
The GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D) is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard packages
• Pb-Free 100-lead TQFP package available

 

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