GS881Z32BT-200I View Datasheet(PDF) - Giga Semiconductor

Part Name

Description

Manufacturer

GS881Z32BT-200I

9Mb Pipelined and Flow Through Synchronous NBT SRAM

Giga Semiconductor 

GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

Min.

Max.

Unit Notes

3.3 V Test Port Input High Voltage

VIHJ3

2.0

VDD3 +0.3

V

1

3.3 V Test Port Input Low Voltage

VILJ3

–0.3

0.8

V

1

2.5 V Test Port Input High Voltage

VIHJ2

0.6 * VDD2

VDD2 +0.3

V

1

2.5 V Test Port Input Low Voltage

VILJ2

–0.3

0.3 * VDD2

V

1

TMS, TCK and TDI Input Leakage Current

IINHJ

–300

1

uA

2

TMS, TCK and TDI Input Leakage Current

IINLJ

–1

100

uA

3

TDO Output Leakage Current

IOLJ

–1

1

uA

4

Test Port Output High Voltage

VOHJ

1.7

—

V 5, 6

Test Port Output Low Voltage

VOLJ

—

0.4

V 5, 7

Test Port Output CMOS High

VOHJC VDDQ – 100 mV

—

V 5, 8

Test Port Output CMOS Low

VOLJC

—

100 mV

V 5, 9

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

2. VILJ ≤ VIN ≤ VDDn

3. 0 V ≤ VIN ≤ VILJn

4. Output Disable, VOUT = 0 to VDDn

5. The TDO output driver is served by the VDDQ supply.

6. IOHJ = –4 mA

7. IOLJ = + 4 mA

8. IOHJC = –100 uA

9. IOHJC = +100 uA

JTAG Port Timing Diagram

TCK

TDI

TMS

TDO

Parallel SRAM input

tTKC

tTKH

tTH

tTS

tTH

tTS

tTKQ

tTH

tTS

tTKL

Rev: 1.04 10/2004

32/39

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2002, GSI Technology

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