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GS881Z32BT-250 View Datasheet(PDF) - Giga Semiconductor

Part NameGS881Z32BT-250 GSI
Giga Semiconductor GSI
Description9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS881Z32BT-250 Datasheet PDF : 39 Pages
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Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Rev: 1.04 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology
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