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GS881Z36BT-200 View Datasheet(PDF) - Giga Semiconductor

Part NameGS881Z36BT-200 GSI
Giga Semiconductor GSI
Description9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS881Z36BT-200 Datasheet PDF : 39 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Rev: 1.04 10/2004
GS881Z18/32/36B NBT SRAM Functional Block Diagram
Specifications cited are subject to change without notice. For latest documentation see
© 2002, GSI Technology
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Functional Description
The GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D) is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard packages
• Pb-Free 100-lead TQFP package available


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