GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
3.3 V Test Port Input High Voltage
3.3 V Test Port Input Low Voltage
2.5 V Test Port Input High Voltage
VIHJ3
VILJ3
VIHJ2
2.0
–0.3
0.6 * VDD2
VDD3 +0.3
0.8
VDD2 +0.3
V
1
V
1
V
1
2.5 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
VILJ2
–0.3
IINHJ
–300
IINLJ
–1
IOLJ
–1
0.3 * VDD2
1
100
1
V
1
uA
2
uA
3
uA
4
Test Port Output High Voltage
VOHJ
1.7
—
V 5, 6
Test Port Output Low Voltage
VOLJ
—
0.4
V 5, 7
Test Port Output CMOS High
VOHJC VDDQ – 100 mV
—
V 5, 8
Test Port Output CMOS Low
VOLJC
—
100 mV
V 5, 9
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDDn
3. 0 V ≤ VIN ≤ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDDQ supply.
6. IOHJ = –4 mA
7. IOLJ = + 4 mA
8. IOHJC = –100 uA
9. IOHJC = +100 uA
JTAG Port AC Test Conditions
Parameter
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDDQ/2
Output reference level
VDDQ/2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG Port AC Test Load
DQ
50Ω
30pF*
VDDQ/2
* Distributed Test Jig Capacitance
Rev: 1.04 11/2004
31/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology