GS8322Z18E-133I View Datasheet(PDF) - Giga Semiconductor

Part Name

Description

Manufacturer

GS8322Z18E-133I

36Mb Pipelined and Flow Through Synchronous NBT SRAM

Giga Semiconductor 

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

JTAG TAP Block Diagram

····· ···

Boundary Scan Register

·

·

·

0

Bypass Register

210

Instruction Register

TDI

TDO

ID Code Register

· 31 30 29 · · · 2 1 0

Control Signals

TMS

TCK

Test Access Port (TAP) Controller

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

Rev: 1.04 11/2004

27/38

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2002, GSI Technology

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