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A42MX09-3CQ100M View Datasheet(PDF) - Microsemi Corporation

Part NameA42MX09-3CQ100M Microsemi
Microsemi Corporation Microsemi
Description40MX and 42MX FPGA Families


A42MX09-3CQ100M Datasheet PDF : 142 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Ceramic Device Resources
User I/Os
Device
CQFP 208-Pin
A42MX36
176
Note: Package Definitions CQFP = Ceramic Quad Flat Pack
40MX and 42MX FPGA Families
CQFP 256-Pin
202
Temperature Grade Offerings
Package
A40MX02
PLCC 44
C, I, M
PLCC 68
C, I, A, M
PLCC 84
PQFP 100
C, I, A, M
PQFP 160
PQFP 208
PQFP 240
VQFP 80
C, I, A, M
VQFP 100
TQFP 176
PBGA 272
CQFP 208
CQFP 256
Note:
C = Commercial
I = Industrial
A = Automotive
M = Military
B = MIL-STD-883 Class B
A40MX04
C, I, M
C, I, M
C, I, A, M
C, I, A, M
C, I, A, M
A42MX09
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
A42MX16
C, I, M
C, I, M
C, I, M
C, I, A, M
C, I, A, M
C, I, A, M
A42MX24
C, I, M
C, I, A, M
C, I, A, M
C, I, A, M
A42MX36
C, I, A, M
C, I, A, M
C, I, M
C, M, B
C, M, B
Speed Grade Offerings
–F
Std
–1
–2
–3
C
I
A
M
B
Note: Refer to the 40MX and 42MX Automotive Family FPGAs datasheet for details on automotive-grade MX offerings.
Contact your local Microsemi SoC Products Group representative for device availability.
Revision 11
iii
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40MX and 42MX FPGA Families

Features
High Capacity
• Single-Chip ASIC Alternative
• 3,000 to 54,000 System Gates
• Up to 2.5 kbits Configurable Dual-Port SRAM
• Fast Wide-Decode Circuitry
• Up to 202 User-Programmable I/O Pins

High Performance
• 5.6 ns Clock-to-Out
• 250 MHz Performance
• 5 ns Dual-Port SRAM Access
• 100 MHz FIFOs
• 7.5 ns 35-Bit Address Decode

HiRel Features
• Commercial, Industrial, Automotive, and Military Temperature Plastic Packages
• Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages
• QML Certification
• Ceramic Devices Available to DSCC SMD

Ease of Integration
• Mixed-Voltage Operation (5.0V or 3.3V for core and I/Os), with PCI-Compliant I/Os
• Up to 100% Resource Utilization and 100% Pin Locking
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Verification Capability with Silicon Explorer II
• Low Power Consumption
• IEEE Standard 1149.1 (JTAG)Boundary Scan Testing

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