A42MX09-3CQ176I View Datasheet(PDF) - Microsemi Corporation

Part Name

Description

Manufacturer

A42MX09-3CQ176I

40MX and 42MX FPGA Families

Microsemi Corporation 

Timing Models

40MX and 42MX FPGA Families

Input Delay

I/O Module

tINYL = 0.62 ns

Predicted

Internal Delays Routing

Delays

tIRD2 = 2.59 ns

Logic Module

tIRD1 = 2.09 ns

tIRD4 = 3.64 ns

tIRD8 = 5.73 ns

tPD = 1.24 ns

tCO = 1.24 ns

tRD1 = 1.28 ns

tRD2 = 1.80 ns

tRD4 = 2.33 ns

tRD8 = 4.93 ns

Output Delay

I/O Module

tDLH = 3.32 ns

tENHZ = 7.92 ns

Array

Clock

tCKH = 4.55 ns

FMAX = 180 MHz

FO = 128

Note: Values are shown for 40MX –3 speed devices at 5.0 V worst-case commercial conditions.

Figure 1-16 • 40MX Timing Model*

Input Delays

I/O Module

tINYL = 0.8 ns

DQ

G

tINH = 0.0 ns

tINSU = 0.3 ns

tINGL = 1.3 ns

Internal Delays

tIRD1 = 2.0 ns1

Combinatorial

Logic Module

tPD=1.2 ns

Sequential

Logic Module

Predicted

Routing

Delays

tRD1 = 0.7 ns

tRD2 = 1.9 ns

tRD4 = 1.4 ns

tRD8 = 2.3 ns

Output Delays

I/O Module

tDLH = 2.5 ns

I/O Module

tDLH = 2.5 ns

Comb.

Logic

Include

DQ

tRD1 = 0.70 ns

DQ

tENHZ = 4.9 ns

G

Array

Clocks

tCKH = 2.70 ns

FMAX = 296 MHz

FO = 32

tSUD = 0.3 ns

tHD = 0.00 ns

tCO = 1.3 ns

tLCO = 5.2 ns (light loads, pad-to-pad)

tOUTH = 0.00 ns

tOUTSU = 0.3 ns

tGLH = 2.6 ns

Notes:

1. Input module predicted routing delay

2. Values are shown for A42MX09 –3 at 5.0 V worst-case commercial conditions.

Figure 1-17 • 42MX Timing Model

Revision 11

1- 27

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