40MX and 42MX FPGA Families
JTAG Mode Activation
The JTAG test logic circuit is activated in the Designer software by selecting Tools -> Device Selection.
This brings up the Device Selection dialog box as shown in Figure 1-14. The JTAG test logic circuit can
be enabled by clicking the "Reserve JTAG Pins" check box. Table 1-5 explains the pins' behavior in
Figure 1-14 • Device Selection Wizard
Table 1-5 • Boundary Scan Pin Configuration and Functionality
BST input; must be terminated to logical HIGH or LOW to avoid floating User I/O
BST input; may float or be tied to HIGH
BST output; may float or be connected to TDI of another device
TRST Pin and TAP Controller Reset
An active reset (TRST) pin is not supported; however, MX devices contain power-on circuitry that resets
the boundary scan circuitry upon power-up. Also, the TMS pin is equipped with an internal pull-up
resistor. This allows the TAP controller to remain in or return to the Test-Logic-Reset state when there is
no input or when a logical 1 is on the TMS pin. To reset the controller, TMS must be HIGH for at least five
Boundary Scan Description Language (BSDL) File
Conforming to the IEEE Standard 1149.1 requires that the operation of the various JTAG components be
documented. The BSDL file provides the standard format to describe the JTAG components that can be
used by automatic test equipment software. The file includes the instructions that are supported,
instruction bit pattern, and the boundary-scan chain order. For an in-depth discussion on BSDL files,
please refer to Actel BSDL Files Format Description application note.
BSDL files are grouped into two categories - generic and device-specific. The generic files assign all user
I/Os as inouts. Device-specific files assign user I/Os as inputs, outputs or inouts.
Generic files for MX devices are available on the Microsemi SoC Product Group's website: