A42MX09-3CQG176 View Datasheet(PDF) - Microsemi Corporation

Part Name

Description

Manufacturer

A42MX09-3CQG176

40MX and 42MX FPGA Families

Microsemi Corporation 

40MX and 42MX FPGA Families

parallel ports are connected to the internal core logic tile and the input, output and control ports of an I/O

buffer to capture and load data into the register to control or observe the logic state of each I/O.

JTAG

TMS

TCK

JTAG

TDI

Boundary Scan Register

Control Logic

Bypass

Register

TAP Controller

Instruction

Decode

Instruction

Register

Output

MUX

TDO

Figure 1-13 • 42MX IEEE 1149.1 Boundary Scan Circuitry

Table 1-3 • Test Access Port Descriptions

Port

Description

TMS

(Test Mode Select)

Serial input for the test logic control bits. Data is captured on the rising edge of the test logic

clock (TCK).

TCK

(Test Clock Input)

Dedicated test logic clock used serially to shift test instruction, test data, and control inputs

on the rising edge of the clock, and serially to shift the output data on the falling edge of the

clock. The maximum clock frequency for TCK is 20 MHz.

TDI

(Test Data Input)

Serial input for instruction and test data. Data is captured on the rising edge of the test logic

clock.

TDO

(Test Data Output)

Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive

state (high impedance) when data scanning is not in progress.

Table 1-4 • Supported BST Public Instructions

Instruction

IR Code Instruction

(IR2.IR0) Type

Description

EXTEST

000 Mandatory Allows the external circuitry and board-level interconnections to be

tested by forcing a test pattern at the output pins and capturing test

results at the input pins.

SAMPLE/PRELOAD 001 Mandatory Allows a snapshot of the signals at the device pins to be captured

and examined during operation

HIGH Z

101

Optional Tristates all I/Os to allow external signals to drive pins. Please refer to

the IEEE Standard 1149.1 specification.

CLAMP

110

Optional Allows state of signals driven from component pins to be determined

from the Boundary-Scan Register. Please refer to the IEEE Standard

1149.1 specification for details.

BYPASS

111 Mandatory Enables the bypass register between the TDI and TDO pins. The test

data passes through the selected device to adjacent devices in the

test chain.

1-14

Revision 11

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