40MX and 42MX FPGA Families
CEQ Values for Microsemi MX FPGAs
Modules (CEQM)3.5
Input Buffers (CEQI)6.9
Output Buffers (CEQO)18.2
Routed Array Clock Buffer Loads (CEQCR)1.4
To calculate the active power dissipated from the complete design, the switching frequency of each part
of the logic must be known. The equation below shows a piece-wise linear summation over all
components.
Power = VCCA2 * [(m x CEQM * fm)Modules +
(n * CEQI * fn)Inputs + (p * (CEQO + CL) * fp)outputs +
0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 +
0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 (2)
where:
m=
n=
p=
q1 =
q2 =
r1 =
r2 =
CEQM =
CEQI =
CEQO =
CEQC =
R
CL =
fm =
fn =
fp
=
fq1 =
fq2 =
Number of logic modules switching at frequency fm
Number of input buffers switching at frequency fn
Number of output buffers switching at frequency fp
Number of clock loads on the first routed array clock
Number of clock loads on the second routed array clock
Fixed capacitance due to first routed array clock
Fixed capacitance due to second routed array clock
Equivalent capacitance of logic modules in pF
Equivalent capacitance of input buffers in pF
Equivalent capacitance of output buffers in pF
Equivalent capacitance of routed array clock in pF
Output load capacitance in pF
Average logic module switching rate in MHz
Average input buffer switching rate in MHz
Average output buffer switching rate in MHz
Average first routed array clock rate in MHz
Average second routed array clock rate in MHz
Fixed Capacitance Values for MX FPGAs (pF)
Device Type
r1
routed_Clk1
r2
routed_Clk2
A40MX02
41.4
N/A
A40MX04
68.6
N/A
A42MX09
118
118
A42MX16
165
165
A42MX24
185
185
A42MX36
220
220
Revision 11
1- 11