Integrated circuits, Transistor, Semiconductors Free Datasheet Search and Download Site


A42MX09-3CQ100M View Datasheet(PDF) - Microsemi Corporation

Part NameA42MX09-3CQ100M Microsemi
Microsemi Corporation Microsemi
Description40MX and 42MX FPGA Families


A42MX09-3CQ100M Datasheet PDF : 142 Pages
First Prev 141 142
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo CA 92656 USA
Within the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at
www.microsemi.com.
© 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of
Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.
5172136-11/5.12
Direct download click here
HOME 'A42MX09-3CQ100M' Search

40MX and 42MX FPGA Families

Features
High Capacity
• Single-Chip ASIC Alternative
• 3,000 to 54,000 System Gates
• Up to 2.5 kbits Configurable Dual-Port SRAM
• Fast Wide-Decode Circuitry
• Up to 202 User-Programmable I/O Pins

High Performance
• 5.6 ns Clock-to-Out
• 250 MHz Performance
• 5 ns Dual-Port SRAM Access
• 100 MHz FIFOs
• 7.5 ns 35-Bit Address Decode

HiRel Features
• Commercial, Industrial, Automotive, and Military Temperature Plastic Packages
• Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages
• QML Certification
• Ceramic Devices Available to DSCC SMD

Ease of Integration
• Mixed-Voltage Operation (5.0V or 3.3V for core and I/Os), with PCI-Compliant I/Os
• Up to 100% Resource Utilization and 100% Pin Locking
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Verification Capability with Silicon Explorer II
• Low Power Consumption
• IEEE Standard 1149.1 (JTAG)Boundary Scan Testing

Share Link : 

한국어     日本語     русский     简体中文     español
@ 2015 - 2018  [ Home  ] [ Privacy Policy ] [ Request Datasheet  ] [ Contact Us ]