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A42MX09-3CQ100M View Datasheet(PDF) - Microsemi Corporation

Part NameA42MX09-3CQ100M Microsemi
Microsemi Corporation Microsemi
Description40MX and 42MX FPGA Families


A42MX09-3CQ100M Datasheet PDF : 142 Pages
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40MX and 42MX FPGA Families
pins or from the internal array and can be used as a secondary register clock, register clear, or output
enable.
CLKB
CLKINB
CLKA
From
Pads
CLKINA
S0
CLKMOD S1
Internal
Signal
CLKO(17)
Clock
Drivers
CLKO(16)
CLKO(15)
Figure 1-7 • Clock Networks of 42MX Devices
CLKO(2)
CLKO(1)
Clock Tracks
QCLKA
QCLKB
*QCLK1IN
Quad
Clock
Modul
S0 S1
QCLK1
QCLK3
Quad
Clock
Modul
S1 S0
QCLKC
QCLKD
*QCLK3IN
*QCLK2IN
Quad
Clock
Modul
QCLK2
QCLK4
Quad
Clock
Modul
*QCLK4IN
S0 S1
S1 S0
Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.
Figure 1-8 • Quadrant Clock Network of A42MX36 Devices
1-6
Revision 11
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40MX and 42MX FPGA Families

Features
High Capacity
• Single-Chip ASIC Alternative
• 3,000 to 54,000 System Gates
• Up to 2.5 kbits Configurable Dual-Port SRAM
• Fast Wide-Decode Circuitry
• Up to 202 User-Programmable I/O Pins

High Performance
• 5.6 ns Clock-to-Out
• 250 MHz Performance
• 5 ns Dual-Port SRAM Access
• 100 MHz FIFOs
• 7.5 ns 35-Bit Address Decode

HiRel Features
• Commercial, Industrial, Automotive, and Military Temperature Plastic Packages
• Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages
• QML Certification
• Ceramic Devices Available to DSCC SMD

Ease of Integration
• Mixed-Voltage Operation (5.0V or 3.3V for core and I/Os), with PCI-Compliant I/Os
• Up to 100% Resource Utilization and 100% Pin Locking
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Verification Capability with Silicon Explorer II
• Low Power Consumption
• IEEE Standard 1149.1 (JTAG)Boundary Scan Testing

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