40MX and 42MX FPGA Families
pins or from the internal array and can be used as a secondary register clock, register clear, or output
enable.
CLKB
CLKINB
CLKA
From
Pads
CLKINA
S0
CLKMOD S1
Internal
Signal
CLKO(17)
Clock
Drivers
CLKO(16)
CLKO(15)
Figure 1-7 • Clock Networks of 42MX Devices
CLKO(2)
CLKO(1)
Clock Tracks
QCLKA
QCLKB
*QCLK1IN
Quad
Clock
Modul
S0 S1
QCLK1
QCLK3
Quad
Clock
Modul
S1 S0
QCLKC
QCLKD
*QCLK3IN
*QCLK2IN
Quad
Clock
Modul
QCLK2
QCLK4
Quad
Clock
Modul
*QCLK4IN
S0 S1
S1 S0
Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.
Figure 1-8 • Quadrant Clock Network of A42MX36 Devices
1-6
Revision 11