Revision 2 (cont’d) The "ProASIC3 FPGAs Package Sizes Dimensions" table is new.
In the "ProASIC3 Ordering Information", the QN package measurements were
updated to include both 0.4 mm and 0.5 mm.
In the "General Description" section, the number of I/Os was updated from 288 to
The "QN68" section is new.
Revision 1 (Feb 2008) In Table 2-2 • Recommended Operating Conditions 1,2, TJ was listed in the
DC and Switching
symbol column and was incorrect. It was corrected and changed to TA.
In Table 2-3 • Flash Programming Limits – Retention, Storage and Operating
Temperature1, Maximum Operating Junction Temperature was changed from
110°C to 100°C for both commercial and industrial grades.
The "PLL Behavior at Brownout Condition" section is new.
In the "PLL Contribution—PPLL" section, the following was deleted:
FCLKIN is the input clock frequency.
In Table 2-21 • Summary of Maximum and Minimum DC Input Levels, the note
was incorrect. It previously said TJ and it was corrected and changed to TA.
In Table 2-115 • ProASIC3 CCC/PLL Specification, the SCLK parameter and note
1 are new.
Table 2-125 • JTAG 1532 was populated with the parameter data, which was not
in the previous version of the document.
In the "VQ100" A3P030 pin table, the function of pin 63 was incorrect and
changed from IO39RSB0 to GDB0/IO38RSB0.
Revision 0 (Jan 2008) This document was previously in datasheet v2.2. As a result of moving to the
handbook format, Actel has restarted the version numbers.
The M7 and M1 device part numbers have been updated in Table 1 • ProASIC3
Product Family, "I/Os Per Package", "Automotive ProASIC3 Ordering
Information", "Temperature Grade Offerings", and "Speed Grade and
Temperature Grade Matrix".
The words "ambient temperature" were added to the temperature range in the
"Automotive ProASIC3 Ordering Information", "Temperature Grade Offerings",
and "Speed Grade and Temperature Grade Matrix" sections.
The TJ parameter in Table 3-2 • Recommended Operating Conditions was
changed to TA, ambient temperature, and table notes 4–6 were added.
In the "Clock Conditioning Circuit (CCC) and PLL" section, the Wide Input
Frequency Range (1.5 MHz to 200 MHz) was changed to (1.5 MHz to 350 MHz).
The "Clock Conditioning Circuit (CCC) and PLL" section was updated.
In the "I/Os Per Package" section, the A3P030, A3P060, A3P125, ACP250, and
A3P600 device I/Os were updated.
Table 3-5 • Package Thermal Resistivities was updated with A3P1000
information. The note below the table is also new.
i, ii, iii,