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M1A3P600-1FGG256YPP View Datasheet(PDF) - Microsemi Corporation

Part NameDescriptionManufacturer
M1A3P600-1FGG256YPP (A3Pxxx) ProASIC3 Flash Family FPGAs with Optional Soft ARM Support Microsemi
Microsemi Corporation Microsemi
M1A3P600-1FGG256YPP Datasheet PDF : 220 Pages
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2 – ProASIC3 DC and Switching Characteristics
General Specifications
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any
other conditions beyond those listed under the Recommended Operating Conditions specified in
Table 2-2 on page 2-2 is not implied.
Table 2-1 • Absolute Maximum Ratings
Symbol
Parameter
Limits
Units
VCC
DC core supply voltage
–0.3 to 1.65
V
VJTAG JTAG DC voltage
–0.3 to 3.75
V
VPUMP Programming voltage
–0.3 to 3.75
V
VCCPLL Analog power supply (PLL)
–0.3 to 1.65
V
VCCI DC I/O output buffer supply voltage
–0.3 to 3.75
V
VMV
DC I/O input buffer supply voltage
–0.3 to 3.75
V
VI
I/O input voltage
–0.3 V to 3.6 V
V
(when I/O hot insertion mode is enabled)
–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower
(when I/O hot-insertion mode is disabled)
TSTG 2
TJ 2
Storage temperature
Junction temperature
–65 to +150
°C
+125
°C
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may
undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.
2. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on
page 3-1 for further information.
3. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating
limits, refer to Table 2-2 on page 2-2.
Revision 13
2-1
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