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M1A3P600-1FGG144I View Datasheet(PDF) - Microsemi Corporation

Part NameDescriptionManufacturer
M1A3P600-1FGG144I (A3Pxxx) ProASIC3 Flash Family FPGAs with Optional Soft ARM Support Microsemi
Microsemi Corporation Microsemi
M1A3P600-1FGG144I Datasheet PDF : 220 Pages
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ProASIC3 Device Family Overview
Bank 0
CCC
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
I/Os
VersaTile
ISP AES
Decryption
User Nonvolatile
FlashROM
Bank 2
Charge Pumps
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
(A3P600 and A3P1000)
Figure 1-2 • ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000)
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic
function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch
interconnections. The versatility of the ProASIC3 core tile as either a three-input lookup table (LUT)
equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile
capability is unique to the Microsemi ProASIC family of third-generation architecture flash FPGAs.
VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed
throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core
utilization is possible for virtually any design.
VersaTiles
The ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core
tiles. The ProASIC3 VersaTile supports the following:
• All 3-input logic functions—LUT-3 equivalent
• Latch with clear or set
• D-flip-flop with clear or set
• Enable D-flip-flop with clear or set
Refer to Figure 1-3 for VersaTile configurations.
LUT-3 Equivalent
X1
X2 LUT-3 Y
X3
D-Flip-Flop with Clear or Set
Data
Y
CLK
D-FF
CLR
Figure 1-3 • VersaTile Configurations
Enable D-Flip-Flop with Clear or Set
Data
Y
CLK
D-FF
Enable
CLR
1-4
Revision 13
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