A10V10B-1CQ100C View Datasheet(PDF) - Actel Corporation

Part Name

Description

Manufacturer

A10V10B-1CQ100C

ACT™ 1 Series FPGAs

Actel Corporation 

ACT™ 1 Series FPGAs

source 10 mA at TTL levels. See Electrical Specifications for

additional I/O buffer specifications.

Device Organization

ACT 1 devices consist of a matrix of logic modules arranged in

rows separated by wiring channels. This array is surrounded

by a ring of peripheral circuits including I/O buffers,

testability circuits, and diagnostic probe circuits providing

real-time diagnostic capability. Between rows of logic

modules are routing channels containing sets of segmented

metal tracks with PLICE antifuses. Each channel has 22

signal tracks. Vertical routing is permitted via 13 vertical

tracks per logic module column. The resulting network allows

arbitrary and flexible interconnections between logic

modules and I/O modules.

Probe Pin

ACT 1 devices have two independent diagnostic probe pins.

These pins allow the user to observe any two internal signals

by entering the appropriate net name in the diagnostic

software. Signals may be viewed on a logic analyzer using

Actel’s Actionprobe® diagnostic tools. The probe pins can

also be used as user-defined I/Os when debugging is finished.

Ordering Information

ACT 1 Array Performance

Temperature and Voltage Effects

Worst-case delays for ACT 1 arrays are calculated in the same

manner as for masked array products. A typical delay

parameter is multiplied by a derating factor to account for

temperature, voltage, and processing effects. However, in an

ACT 1 array, temperature and voltage effects are less

dramatic than with masked devices. The electrical

characteristics of module interconnections on ACT 1 devices

remain constant over voltage and temperature fluctuations.

As a result, the total derating factor from typical to

worst-case for a standard speed ACT 1 array is only 1.19 to 1,

compared to 2 to 1 for a masked gate array.

Logic Module Size

Logic module size also affects performance. A mask

programmed gate array cell with four transistors usually

implements only one logic level. In the more complex logic

module (similar to the complexity of a gate array macro) of

an ACT 1 array, implementation of multiple logic levels

within a single module is possible. This eliminates interlevel

wiring and associated RC delays. The effect is termed “net

compression.”

A1010 B – 2

PL

84

C

Application (Temperature Range)

C = Commercial (0 to +70°C)

I = Industrial (–40 to +85°C)

M = Military (–55 to +125°C)

B = MIL-STD-883

Package Lead Count

Package Type

PL = Plastic J-Leaded Chip Carriers

PQ = Plastic Quad Flatpacks

CQ = Ceramic Quad Flatpack

PG = Ceramic Pin Grid Array

VQ = Very Thin Quad Flatpack

Speed Grade

Blank = Standard Speed

–1 = Approximately 15% faster than Standard

–2 = Approximately 25% faster than Standard

–3 = Approximately 35% faster than Standard

Die Revision

B = 1.0 micron CMOS Process

Part Number

A1010 = 1200 Gates (5 V)

A1020 = 2000 Gates (5 V)

A10V10 = 1200 Gates (3.3 V)

A10V20 = 2000 Gates (3.3 V)

1-285

Share Link: