A10V10B-1PG68I View Datasheet(PDF) - Actel Corporation

Part Name

Description

Manufacturer

A10V10B-1PG68I

ACT™ 1 Series FPGAs

Actel Corporation 

ACT 1 Timing Module*

Input Delay

Internal Delays

I/O Module

tINYL = 3.1 ns

tIRD2 = 1.4 ns

Logic Module

Predicted

Routing

Delays

Output Delay

I/O Module

tIRD1 = 0.9 ns

tIRD4 = 3.1 ns

tIRD8 = 6.6 ns

tPD = 2.9 ns

tCO = 2.9 ns

tRD1 = 0.9 ns

tRD2 = 1.4 ns

tRD4 = 3.1 ns

tRD8 = 6.6 ns

tDLH = 6.7 ns

tENHZ = 11.6 ns

ARRAY

CLOCK

tCKH = 5.6 ns

FMAX = 70 MHz

FO = 128

* Values shown for ACT 1 ‘–3 speed’ devices at worst-case commercial conditions.

Predictable Performance: Tight Delay

Distributions

Propagation delay between logic modules depends on the

resistive and capacitive loading of the routing tracks, the

interconnect elements, and the module inputs being driven.

Propagation delay increases as the length of routing tracks,

the number of interconnect elements, or the number of

inputs increases.

From a design perspective, the propagation delay can be

statistically correlated or modeled by the fanout (number of

loads) driven by a module. Higher fanout usually requires

some paths to have longer routing tracks.

The ACT 1 family delivers a very tight fanout delay

distribution. This tight distribution is achieved in two ways: by

decreasing the delay of the interconnect elements and by

decreasing the number of interconnect elements per path.

Actel’s patented PLICE antifuse offers a very low

resistive/capacitive interconnect. The ACT 1 family’s

antifuses, fabricated in 1.0 micron lithography, offer nominal

levels of 200 ohms resistance and 7.5 femtofarad (fF)

capacitance per antifuse.

The ACT 1 fanout distribution is also tight due to the low

number of antifuses required for each interconnect path. The

ACT 1 family’s proprietary architecture limits the number of

antifuses per path to a maximum of four, with 90% of

interconnects using two antifuses.

Timing Characteristics

Timing characteristics for ACT 1 devices fall into three

categories: family dependent, device dependent, and design

dependent. The input and output buffer characteristics are

common to all ACT 1 family members. Internal routing delays

are device dependent. Design dependency means actual delays

are not determined until after placement and routing of the

user design is complete. Delay values may then be determined

by using the DirectTime Analyzer utility or performing

simulation with post-layout delays.

Critical Nets and Typical Nets

Propagation delays are expressed only for typical nets, which

are used for initial design performance evaluation. Critical

net delays can then be applied to the most time-critical paths.

Critical nets are determined by net property assignment prior

to placement and routing. Up to 6% of the nets in a design may

be designated as critical, while 90% of the nets in a design are

typical.

Long Tracks

Some nets in the design use long tracks. Long tracks are

special routing resources that span multiple rows, columns, or

modules. Long tracks employ three and sometimes four

antifuse connections. This increases capacitance and

resistance, resulting in longer net delays for macros

connected to long tracks. Typically, up to 6% of nets in a fully

utilized device require long tracks. Long tracks contribute

approximately 5 ns to 10 ns delay. This additional delay is

represented statistically in higher fanout (FO=8) routing

delays in the data sheet specifications section.

1-292

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