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9403A 데이터 시트보기 (PDF) - Fairchild Semiconductor

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9403A First-In First-Out (FIFO) Buffer Memory Fairchild
Fairchild Semiconductor Fairchild
9403A Datasheet PDF : 16 Pages
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Functional Description (Continued)
EXPANSION
Vertical ExpansionThe 9403A may be vertically
expanded to store more words without external parts. The
interconnection is necessary to form a 46-word by 4-bit
FIFO are shown in Figure 4. Using the same technique,
and FIFO of (15n + 1)-words by 4-bits can be constructed,
where n is the number of devices. Note that expansion
does not sacrifice any of the 9403As flexibility for serial/
parallel input and output.
FIGURE 4. A Vertical Expansion Scheme
Horizontal ExpansionThe 9403A can also be horizon-
tally expanded to store long words (in multiples of four bits)
without external logic. The interconnections necessary to
form a 16-word by 12-bit FIFO are shown in Figure 5.
Using the same technique, any FIFO of 16 words by 4n bits
can be constructed, where n is the number of devices. The
IRF output of the right most device (most significant device)
is connected to the TTS inputs of all devices. Similarly, the
ORE output of the most significant device is connected to
the TOS inputs of all devices. As in the vertical expansion
scheme, horizontal expansion does not sacrifice any of the
9403As flexibility for serial/parallel input and output.
Horizontal and Vertical ExpansionThe 9403A can be
expanded in both the horizontal and vertical directions
without any external parts and without sacrificing any of its
FIFOs flexibility for serial/parallel input and output. The
interconnections necessary to form a 31-word by 16-bit
FIFO are shown in Figure 6. Using the same technique,
any FIFO of (15m + 1)-words by (4n)-bits can be con-
structed, where m is the number of devices in a column
and n is the number of devices in a row. Figure 7 and Fig-
ure 8 show the timing diagrams for serial data entry and
extraction for the 31-word by 16-bit FIFO shown in Figure
6. The final position of data after serial insertion of 496 bits
into the FIFO array of Figure 6 is shown in Figure 9.
Interlocking CircuitryMost conventual FIFO designs
provide status signals analogous to IRF and ORE. How-
ever, when these devices are operated in arrays, variations
in unit to unit operating speed require external gating to
assure all devices have completed an operation. The
9403A incorporates simple but effective master/slave
interlocking circuitry to eliminate the need for external gat-
ing.
In the 9403A array of Figure 6 devices 1 and 5 are defined
as row mastersand the other devices are slaves to the
master in their row. No slave in a given row will initialize its
Input Register until it has received LOW on its IES input
from a row master or a slave of higher priority.
In a similar fashion, the ORE outputs of slaves will not go
HIGH until their OES inputs have gone HIGH. This inter-
locking scheme ensures that new input data may be
accepted by the array when the IRF output of the final
slave in that row goes HIGH and that output data for the
array may be extracted when the ORE of the final slave in
the output row goes HIGH.
The row master is established by connecting its IES input
to ground while a slave receives it IES input from the IRF
output of the next higher priority device. When an array of
9403A FIFOs is initialized with a LOW on the MR inputs of
all devices, the IRF outputs of all devices will be HIGH.
Thus, only the row master receives a LOW on the IES input
during initialization. Figure 10 is a conceptual logic diagram
of the internal circuitry which determines master/slave
operation. Whenever MR and IES are LOW, the Master
Latch is set. Whenever TTS goes LOW the Request Initial-
ization Flip-Flop will be set. If the Master Latch is HIGH, the
input Register will be immediately initialized and the
Request Initialization Flip-Flop reset. If the Master Latch is
reset, the Input Register is not initialized until IES goes
LOW. In array operation, activating the TTS initiates a rip-
ple input register initialization from the row master to the
last slave.
A similar operation takes place for the output register.
Either a TOS or TOP input initiates a load-from-stack oper-
ation and sets the ORE Request Flip-Flop. If the Master
Latch is set, the last Output Register Flip-Flop is set and
ORE goes HIGH. If the Master latch is reset, the ORE out-
put will be LOW until an OES input is received.
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