As shown in the block diagram the 49403A consists of
1. An Input Register with parallel and serial data inputs as
well as control inputs and outputs for input handshak-
ing and expansion.
2. A 4-bit wide, 14-word deep fall-through stack with self-
contained control logic.
3. An Output Register with parallel and serial data outputs
as well as control inputs and outputs for output hand-
shaking and expansion.
Since these three sections operate asynchronously and
almost independently, they will be described separately
INPUT REGISTER (DATA ENTRY)
The Input Register can receive data in either bit-serial or in
4-bit parallel form. It stores this data until it is sent to the
fall-through stack and generates the necessary status and
Figure 1 is a conceptual logic diagram of the input section.
As described later, this 5-bit register is initialized by setting
the F3 flip-flop and resetting the other flip-flops. The Q out-
put of the last flip-flop (FC) is brought out as the “Input
Register Full” output (IRF). After initialization this output is
Parallel Entry—A HIGH on the PL input loads the D0-D3
inputs into the F0-F3 flip-flops and sets the FC flip-flop. This
forces the IRF output LOW indicating that the input register
is full. During parallel entry, the CPSI input must be LOW. If
parallel expansion is not being implemented, IES must be
LOW to establish row mastership (see Expansion section).
Serial Entry—Data on the DS input is serially entered into
the F3, F2, F1, F0, FC shift register on each HIGH-to-LOW
transition of the CPSI clock input, provided IES and PL are
After the fourth clock transition, the four data bits are
located in the four flip-flops, F0-F3. The FC flip-flop is set,
forcing the IRF output LOW and internally inhibiting CPSI
clock pulses from affecting the register, Figure 2 illustrates
the final positions in a 9403A resulting from a 64-bit serial
bit train. B0 is the first bit, B63 the last bit.
FIGURE 1. Conceptual Input Section
FIGURE 2. Final Positions in a 9403A Resulting from a 64-Bit Serial Train