Philips Semiconductors
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3
VARIABLE CLOCK4
33MHz CLOCK
SYMBOL FIGURE
PARAMETER
MIN
MAX
MIN
MAX UNIT
tLHLL
29
tAVLL
29
tLLAX
29
tLLIV
29
tLLPL
29
tPLPH
29
tPLIV
29
tPXIX
29
tPXIZ
29
tAVIV
29
tPLAZ
29
Data Memory
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
2tCLCL–40
21
ns
tCLCL–25
5
ns
tCLCL–25
ns
4tCLCL–65
55
ns
tCLCL–25
5
ns
3tCLCL–45
45
ns
3tCLCL–60
30
ns
0
0
ns
tCLCL–25
5tCLCL–80
10
5
ns
70
ns
10
ns
tRLRH
30, 31
tWLWH
30, 31
tRLDV
30, 31
tRHDX
30, 31
tRHDZ
30, 31
tLLDV
30, 31
tAVDV
30, 31
tLLWL
30, 31
tAVWL
30, 31
tQVWX
30, 31
tWHQX
30, 31
tQVWH
31
tRLAZ
30, 31
tWHLH
30, 31
External Clock
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
6tCLCL–100
82
ns
6tCLCL–100
82
ns
5tCLCL–90
60
ns
0
0
ns
2tCLCL–28
32
ns
8tCLCL–150
90
ns
9tCLCL–165
105
ns
3tCLCL–50
3tCLCL+50
40
140
ns
4tCLCL–75
45
ns
tCLCL–30
0
ns
tCLCL–25
5
ns
7tCLCL–130
80
ns
0
0
ns
tCLCL–25
tCLCL+25
5
55
ns
tCHCX
33
tCLCX
33
tCLCH
33
tCHCL
33
Shift Register
High time
Low time
Rise time
Fall time
0.38tCLCL
tCLCL–tCLCX
ns
0.38tCLCL
tCLCL–tCHCX
ns
5
ns
5
ns
tXLXL
32
Serial port clock cycle time
12tCLCL
360
ns
tQVXH
32
Output data setup to clock rising edge
10tCLCL–133
167
ns
tXHQX
32
Output data hold after clock rising edge
2tCLCL–80
ns
tXHDX
32
Input data hold after clock rising edge
0
0
ns
tXHDV
32
Clock rising edge to input data valid
10tCLCL–133
167
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. For frequencies equal or less than 16MHz, see 16MHz “AC Electrical Characteristics”, page 38.
5. Parts are guaranteed to operate down to 0Hz.
1999 Apr 01
39