NSE-20G™ Standard Product Data Sheet
Preliminary
9.1.5
9.1.6
9.2
9.2.1
9.3
The DRU recovers data and outputs a ten-bit word synchronized with a line rate divided by ten,
gated clock to allow frequency deviations between the data source and the local oscillator. The
output clock is not a recovered clock. The DRU accumulates 10 data bits and outputs them on the
next clock edge. If 10-bits are not available for transfer at a given clock cycle, the output clock is
gated.
The DRU provides moderate high frequency jitter tolerance suitable for inter-chip serial link
applications. It can support frequency deviations up to ±100ppm.
There are 32 instances of the DRU on the NSE-20G.
Parallel to Serial Converter (PISO)
The PISO is a parallel-to-serial converter designed for high-speed transmit operation, supporting
up to 777.6 Mbit/s.
There are 32 instances of the PISO on the NSE-20G.
Clock Synthesis Unit (CSU)
The CSU is a fully integrated clock synthesis unit. It generates low jitter multi-phase differential
clocks at 777.6 MHz for the use by the transmitter.
There are two instances of the CSU on the NSE-20G.
Receive 8B/10B Frame Aligner (R8TD)
The Receive 8B/10B serial SBI336S Bus frame aligner, R8TD, frames to the receive stream to
find 8B/10B character boundaries. It also contains a FIFO to bridge between the timing domain of
the receive LVDS links and the system clock timing domain. The R8TD blocks perform framing
and elastic store functions on data retrieved from the receive LVDS links, RP[x]/RN[x].
FIFO Buffer
The FIFO buffer sub-block provides isolation between the timing domains of the associated
receive LVDS link and that of the system clock, SYSCLK. Data with arbitrary alignment to the
8B/10B characters, are written into a 10-bit by 24-word deep FIFO at the link clock rate. Data is
read from the FIFO at every SYSCLK cycle.
Transmit 8B/10B Encoder (T8TE)
The Transmit 8B/10B Encoder blocks, T8TE, construct an 8B/10B character stream from an
incoming translated SBI336 or TelecomBus carrying an STS-12/STM-4 equivalent channelized
stream. The T8TE block corrects the running disparity of an 8B/10B character stream and buffers
data in a FIFO before transmission to the transmit serializer block. A total of 32 T8TE blocks are
instantiated in the NSE-20G device.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
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Document ID: PMC-2000170, Issue 3