Clock Pulse Input 3-STATE
Output Enable Input 3-STATE
The VHCT574A consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the state
of their individual D inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP) transi-
H HIGH Voltage Level
L LOW Voltage Level
Z High Impedance
tion. With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.