74VHC174T View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

74VHC174T

HEX D-TYPE FLIP FLOP WITH CLEAR

STMicroelectronics 

®

74VHC174

HEX D-TYPE FLIP FLOP WITH CLEAR

s HIGH SPEED:

fMAX =175 MHz (TYP.) at VCC = 5V

s LOW POWER DISSIPATION:

ICC = 4 µA (MAX.) at TA = 25 oC

s HIGH NOISE IMMUNITY:

VNIH = VNIL = 28% VCC (MIN.)

s POWER DOWN PROTECTION ON INPUTS

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8 mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC (OPR) = 2V to 5.5V

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 174

s IMPROVED LATCH-UP IMMUNITY

s LOW NOISE: VOLP = 0.8V (Max.)

DESCRIPTION

The 74VHC174 is an advanced high-speed

CMOS HEX D-TYPE FLIP FLOP WITH CLEAR

fabricated with sub-micron silicon gate and

double-layer metal wiring C2MOS technology.

Information signals applied to D inputs are

PRELIMINARY DATA

M

(Micro Package)

T

(TSSOP Package)

ORDER CODES :

74VHC174M

74VHC174T

transfered to the Q outputs on the positive going

edge of the clock pulse.

When the CLEAR input is held low, the Q outputs

are held low independently of the other inputs.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

June 1999

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