BR93LC56FV View Datasheet(PDF) - ROHM Semiconductor

Part Name

Description

Manufacturer

BR93LC56FV

2,048-Bit Serial Electrically Erasable PROM

ROHM Semiconductor 

Memory ICs

BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV

(6) Connecting DI and DO directly

The BR93LC56 / F / FV have an independent input pin

(DI) and output pin (DO). These are treated as individ-

ual signals on the timing chart but can be controlled

through one control line.Control can be initiated on a

single control line by inserting a resistor R betweeen

the [DI] pin and [DO] pin.

µ-COM

BR93LC56

I / O PORT

DI

R

DO

Fig. 11 Common connections for

the DI and DO control line

1) Data collision between the µ-COM output and the

DO output

Within the input and output timing of the BR93LC56 / F

/ FV, the drive from the µ-COM output to the DI input

and a signal output from the DO output can be emitted

at the same time. This happens only for the 1 clock

cycle (a dummy bit “0” is output to the DO pin) which

acquires the A0 address data during a read cycle.

When the address data A0 = 1, the µ-COM output

becomes a direct current source for the DO pin.

The resistor R is the only resistance which limits this

current. Therefore, a resistor with a value which satis-

fies the µ-COM and the BR93LC56 / F / FV current

capacity is required. When using a single control line,

when a dummy bit “0” is output to the DO, the µ-COM

I / O address data A0 is also output. Therefore, the

dummy bit cannot be detected.

2) Feedback to the DI input from the DO output

Data is output from the DO pin and then feeds back

into the DI input through the resistor R. This happens

when:

· DO data is output during a read operation

· A READY / BUSY signal is output during WRITE or

WRAL operation

Such feedback does not cause problems in the basic

operation of the BR93LC56 / F / FV.

The µ-COM input level must be adequately maintained

for the voltage drop at R which is caused by the total

input leakage current for the µ-COM and the BR93-

LC56 / F / FV.

In the state in which SK is input, when the READY /

BUSY function is used, make sure that CS is dropped

to LOW within four clock pulses of the output of the

READY signal HIGH and the standby mode is restored.

For input after the fifth clock pulse, the READY HIGH

will be taken as the start bit and WDS or some other

mode will be activated, depending on the DI state.

11

Share Link: