DatasheetQ Logo
Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

74LV107PW View Datasheet(PDF) - Philips Electronics

Part Name
Description
Manufacturer
74LV107PW Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
Product specification
74LV107
FEATURES
Wide operating: 1.0 to 5.5 V
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25°C
Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
Tamb = 25°C
Output capability: standard
ICC category: flip-flops
DESCRIPTION
The 74LV107 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT107.
The 74LV107 is a dual negative-edge triggered JK-type flip-flop
featuring individual J, K, clock (nCP) and reset (nR) inputs; also
complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to the
HIGH-to-LOW clock transition for predictable operation.
The reset (nR) is an asynchronous active LOW input. When LOW, it
overrides the clock and data inputs, forcing the Q output LOW and
the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
nCP to nQ
nCP to nQ
nR to nQ, nQ
CL = 15 pF;
VCC = 3.3 V
fmax
Maximum clock frequency
CI
Input capacitance
CPD
Power dissipation capacitance per flip-flop VI = GND to VCC1
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi (CL × VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
ȍ (CL × VCC2 × fo) = sum of the outputs.
TYPICAL
15
15
15
77
3.5
30
UNIT
ns
MHz
pF
pF
ORDERING INFORMATION
PACKAGES
14-Pin Plastic DIL
14-Pin Plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +125°C
74LV107 N
–40°C to +125°C
74LV107 D
–40°C to +125°C
74LV107 DB
–40°C to +125°C
74LV107 PW
NORTH AMERICA
74LV107 N
74LV107 D
74LV107 DB
74LV107PW DH
PKG. DWG. #
SOT27-1
SOT108-1
SOT337-1
SOT402-1
PIN CONFIGURATION
1J 1
1Q 2
1Q 3
1K 4
2Q 5
2Q 6
GND 7
14 VCC
13 1R
12 1CP
11 2K
10 2R
9 2CP
8 2J
SV00497
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 8, 4, 11 1J, 2J, 1K, 2K Synchronous inputs; flip-flops 1 and 2
2, 6
1Q, 2Q Complement flip-flop outputs
3, 5
1Q, 2Q True flip-flop outputs
7
GND
Ground (0 V)
12, 9
1CP, 2CP
Clock input
(HIGH-to-LOW, edge-triggered)
13, 10
1R, 2R
Asynchronous reset inputs
(active LOW)
14
VCC
Positive supply voltage
1998 Apr 20
2
853–1904 19255
 

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]