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74LCX240CW View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
Manufacturer
74LCX240CW Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
February 1994
Revised March 2005
74LCX240
Low Voltage Octal Buffer/Line Driver with
5V Tolerant Inputs and Outputs
General Description
The LCX240 is an inverting octal buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver. The
device is designed for low voltage (2.5V or 3.3V) VCC appli-
cations with capability of interfacing to a 5V signal environ-
ment.
The LCX240 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs
s 2.3V–3.6V VCC specifications provided
s 6.5 ns tPD max (VCC 3.3V), 10 PA ICC max
s Power-down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s r24 mA output drive (VCC 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model ! 2000V
Machine model ! 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
Package
Number
Package Description
74LCX240WM
M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LCX240SJ
M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX240MSA
MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74LCX240MTC
MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LCX240MTCX_NL MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
(Note 2)
Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 2: _NLindicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Diagram
Connection Diagram
© 2005 Fairchild Semiconductor Corporation DS011993
www.fairchildsemi.com
 

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