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74HC73U 查看數據表(PDF) - Philips Electronics

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74HC73U Dual JK flip-flop with reset; negative-edge trigger Philips
Philips Electronics Philips
74HC73U Datasheet PDF : 21 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Table 8: Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 8.
Symbol Parameter
Conditions
trem
removal time nR to nCP
tsu
set-up time nJ, nK to nCP
th
hold time nJ, nK to nCP
fmax
maximum clock frequency
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL × VCC2 × fo) = sum of outputs.
Min
Typ
Max Unit
120
-
-
ns
24
-
-
ns
20
-
-
ns
120
-
-
ns
24
-
-
ns
20
-
-
ns
3
-
-
ns
3
-
-
ns
3
-
-
ns
4.0
-
-
MHz
20
-
-
MHz
24
-
-
MHz
9397 750 13815
Product data sheet
Rev. 03 — 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12 of 21
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