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74F399 查看數據表(PDF) - Philips Electronics

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74F399 Quad 2-Port Register Philips
Philips Electronics Philips
74F399 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Philips Semiconductors
Registers
Product specification
74F398*,74F399
74F398 Quad 2-Port Register with True and Complementary Outputs
74F399 Quad 2-Port Register
FEATURES
Select inputs from two data sources
Fully positive edge-triggered
Both True and Complementary outputs–74F398
DESCRIPTION
The 74F398 and 74F399 are the logical equivalent of a quad 2-input
multiplexer feeding into four edge-triggered flip-flops. A common
Select input determines which of two 4-bit words is accepted. The
selected data enters the flip-flops on the rising edge of the clock.
The 74F399 is the 16-pin version of the 74F398, with only the true
(Qn) outputs of the flip-flops available.
The 74F398 and 74F399 are high speed quad 2-port registers. They
select 4 bits of data from either of two sources (Ports) under control
of a common select input (S). The selected data is transferred to a
4-bit output register synchronous with the Low-to-High transition of
the Clock input (CP). The 4-bit D-type output register is fully
edge-triggered. The Data inputs (I0n, I1n) and Select input (S) must
be stable only a setup time prior to and hold time after the
Low-to-High transition of the Clock input for predictable operation.
The 74F398 has both Q and Q outputs.
TYPE
74F398
74F399
TYPICAL fMAX
120MHz
120MHz
TYPICAL SUPPLY CURRENT
(TOTAL)
25mA
22mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
16-pin plastic DIP
N74F399N
16-pin plastic SO
N74F399D
PKG DWG #
SOT38-4
SOT109-1
PIN CONFIGURATION – 74F398
S1
Qa 2
Qa 3
I0a 4
I1a 5
I1b 6
I0b 7
Qb 8
Qb 9
GND 10
20 VCC
19 Qd
18 Qd
17 I0d
16 I1d
15 I1c
14 I0c
13 Qc
12 Qc
11 CP
SF00947
PIN CONFIGURATION – 74F399
S1
Qa 2
I0a 3
I1a 4
I1b 5
I0b 6
Qb 7
GND 8
16 VCC
15 Qd
14 I0d
13 I1d
12 I1c
11 I0c
10 Qc
9 CP
SF00951
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
I0a, I0b, I0c, I0d Data inputs from source 0
I1a, I1b, I1c, I1d Data inputs from source 1
S
Common Select input
CP
Clock input (active rising edge)
Qa, Qb, Qc, Qd Register true outputs
Qa, Qb, Qc, Qd Register complementary outputs (74F398)
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
74F (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
50/33
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
1.0mA/20mA
* Discontinued part. Please see the Discontinued Products List..
1999 Jan 08
2
853–0028 20616
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