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74F114SC View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
Manufacturer
74F114SC Datasheet PDF : 6 Pages
1 2 3 4 5 6
Unit Loading/Fan Out
Pin Names
Description
J1, J2, K1, K2
CP
Data Inputs
Clock Pulse Input (Active Falling Edge)
CD
SD1, SD2
Q1, Q2, Q1, Q2
Direct Clear Input (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/8.0
1.0/10.0
1.0/5.0
50/33.3
Truth Table
Input IIH/IIL
Output IOH/IOL
20 µA/0.6 mA
20 µA/4.8 mA
20 µA/6.0 mA
20 µA/3.0 mA
1 mA/20 mA
Inputs
Outputs
SD
CD
CP
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H
H
H
H
H
H

h
l
h
Q0
Q0
h
L
H
 H
H
h
l
H
L
 H
H
l
l
Q0
Q0
H (h) = HIGH Voltage Level
L (h) = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW Clock Transition
Q0 (Q0) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram
(one half shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
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