74F112 View Datasheet(PDF) - Fairchild Semiconductor

Part Name

Description

Manufacturer

74F112

Dual JK Negative Edge-Triggered Flip-Flop

Fairchild Semiconductor 

April 1988

Revised September 2000

74F112

Dual JK Negative Edge-Triggered Flip-Flop

General Description

The 74F112 contains two independent, high-speed JK flip-

flops with Direct Set and Clear inputs. Synchronous state

changes are initiated by the falling edge of the clock. Trig-

gering occurs at a voltage level of the clock and is not

directly related to the transition time. The J and K inputs

can change when the clock is in either state without affect-

ing the flip-flop, provided that they are in the desired state

during the recommended setup and hold times relative to

the falling edge of the clock. A LOW signal on SD or CD

prevents clocking and forces Q or Q HIGH, respectively.

Simultaneous LOW signals on SD and CD force both Q and

Q HIGH.

Asynchronous Inputs:

LOW input to SD sets Q to HIGH level

LOW input to CD sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on CD and SD makes both Q

and Q HIGH

Ordering Code:

Order Number Package Number

Package Description

74F112SC

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

74F112SJ

M16D

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74F112PC

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

© 2000 Fairchild Semiconductor Corporation DS009472

www.fairchildsemi.com

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