74ALVCH16540DGG View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

74ALVCH16540DGG

2.5V/3.3V 16-bit buffer/line driver, inverting, 5V input tolerant (3-State)

Philips Electronics 

Philips Semiconductors

16-bit buffer/line driver, inverting,

5V input tolerant (3-State)

Product specification

74ALVCH16540

FEATURES

• Wide supply voltage range of 1.2 V to 3.6 V

• Complies with JEDEC standard no. 8-1A

• CMOS low power consumption

• MULTIBYTETM flow-through standard pin-out architecture

• Low inductance multiple VCC and ground pins for minimum noise

and ground bounce

• Direct interface with TTL levels

• Bus hold on all data inputs eliminates the need for external pull-up

resistors to hold unused inputs

• Output drive capability 50Ω transmission lines @ 85°C

PIN CONFIGURATION

1OE1 1

1Y0 2

1Y1 3

GND 4

1Y2 5

1Y3 6

VCC 7

1Y4 8

1Y5 9

GND 10

48 1OE2

47 1A0

46 1A1

45 GND

44 1A2

43 1A3

42 VCC

41 1A4

40 1A5

39 GND

DESCRIPTION

The 74ALVCH16540 is a high-performance, low-power, low-voltage,

Si-gate CMOS device, superior to most advanced CMOS

compatible TTL families.

The 74ALVCH16540 is a 16-bit inverting buffer/line driver with

3-State outputs. The 3-State outputs are controlled by the output

enable inputs 1OEn and 2OEn. A HIGH on nOEn causes the outputs

to assume a high impedance OFF-state.

Active bus hold circuitry is provided to hold unused or floating data

inputs at a valid logic level. This feature eliminates the need for

external pull-up or pull-down resistors. The device can be used as

four 4-bit buffers, two 8-bit buffers or one 16-bit buffer.

1Y6 11

1Y7 12

2Y0 13

2Y1 14

GND 15

2Y2 16

2Y3 17

VCC 18

2Y4 19

2Y5 20

38 1A6

37 1A7

36 2A0

35 2A1

34 GND

33 2A2

32 2A3

31 VCC

30 2A4

29 2A5

GND 21

28 GND

2Y6 22

27 2A6

2Y7 23

26 2A7

2OE1 24

25 2OE2

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns

SYMBOL

PARAMETER

CONDITIONS

SW00108

TYPICAL

tPHL/tPLH

Propagation delay

1An to 1Yn;

2An to 2Yn

CL = 50pF

VCC = 3.3V

CL = 30pF

VCC = 2.5V

1.8

1.8

CI

Input capacitance

5.0

Outputs enabled

26

CPD

Power dissipation capacitance per buffer

VI = GND to VCC1

Outputs disabled

5

NOTES:

1. CPD is used to determine the dynamic power dissipation (PD in mW):

PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where:

fi = input frequency in MHz; CL = output load capacitance in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

S (CL × VCC2 × fo) = sum of outputs.

UNIT

ns

ns

pF

pF

pF

ORDERING INFORMATION

PACKAGES

48-Pin Plastic SSOP Type III

48-Pin Plastic TSSOP Type II

TEMPERATURE RANGE OUTSIDE NORTH AMERICA

–40°C to +85°C

74ALVCH16540 DL

–40°C to +85°C

74ALVCH16540 DGG

NORTH AMERICA

ACH16540 DL

ACH16540 DGG

DWG NUMBER

SOT370-1

SOT362-1

1997 Aug 11

2

853-2020 18266

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