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74ALVC162835ADGG View Datasheet(PDF) - Philips Electronics

Part Name74ALVC162835ADGG Philips
Philips Electronics Philips
Description18-bit registered driver with 30Ω termination resistors (3-State)
74ALVC162835ADGG Datasheet PDF : 12 Pages
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Philips Semiconductors
18-bit registered driver with 30termination resistors
(3-State)
Product specification
74ALVC162835A
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive ± 12 mA at 3.0 V
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
Output drive capability 50 transmission lines @ 85°C
Integrated 30 W termination resistors
Diode clamps to VCC and GND on all inputs
Input diodes to accommodate strong drivers
DESCRIPTION
The 74ALVC162835A is an 18-bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
When LE is HIGH, the A to Y data flow is transparent. When LE is
LOW and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
The 74ALVC162835A is designed with 30 W_series resistors in both
HIGH or LOW output stages.
When OE is LOW the outputs are active. When OE is HIGH, the
outputs go to the high impedance OFF-state. Operation of the OE
input does not affect the state of the latch/flip -flop.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
PIN CONFIGURATION
NC 1
NC 2
Y1 3
GND 4
Y2 5
Y3 6
VCC 7
Y4 8
Y5 9
Y6 10
GND 11
Y7 12
Y8 13
Y9 14
Y10 15
Y11 16
Y12 17
GND 18
Y13 19
Y14 20
Y15 21
VCC 22
Y16 23
Y17 24
GND 25
Y18 26
OE 27
LE 28
56 GND
55 NC
54 A1
53 GND
52 A2
51 A3
50 VCC
49 A4
48 A5
47 A6
46 GND
45 A7
44 A8
43 A9
42 A10
41 A11
40 A12
39 GND
38 A13
37 A14
36 A15
35 VCC
34 A16
33 A17
32 GND
31 A18
30 CP
29 GND
SH00188
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
Propagation delay
tPHL/tPLH
An to Yn;
LE to Yn;
VCC = 3.3 V, CL = 50 pF
2.9
3.5
CP to Yn
3.3
fmax
Maximum clock frequency
VCC = 3.3 V, CL = 50 pF
240
CI
Input capacitance
4.0
CI/O
Input/Output capacitance
8.0
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
transparent mode
Output enabled
10
Output disabled
3
Clocked mode
Output enabled
21
Output disabled
15
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
UNIT
ns
MHz
pF
pF
pF
2000 Jun 20
2
853–2191 23931
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