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74ALS74 Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear Fairchild
Fairchild Semiconductor Fairchild
74ALS74 Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
September 1986
Revised February 2000
DM74ALS74A
Dual D Positive-Edge-Triggered Flip-Flop
with Preset and Clear
General Description
The DM74ALS74A contains two independent positive
edge-triggered flip-flops. Each flip-flop has individual D,
clock, clear and preset inputs, and also complementary Q
and Q outputs.
Information at input D is transferred to the Q output on the
positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive going
pulse. When the clock input is at either the HIGH or LOW
level, the D input signal has no effect.
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of low level signal.
Features
s Switching specifications at 50 pF
s Switching specifications guaranteed over full tempera-
ture and VCC range
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s Functionally and pin-for-pin compatible with Schottky
and LS TTL counterpart
s Improved AC performance over LS74 at approximately
half the power
Ordering Code:
Order Number Package Number Package Description
DM74ALS74AM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS74ASJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS74AN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
PR CLR CLK D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X H (Note 1) H (Note 1)
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q0
Q0
L = LOW State
H = HIGH State
X = Don't Care
↑ = Positive Edge Transition
Q0 = Previous Condition of Q
Note 1: This condition is nonstable; it will not persist when preset and clear
inputs return to their inactive (HIGH) level. The output levels in this condi-
tion are not guaranteed to meet the VOH specification.
© 2000 Fairchild Semiconductor Corporation DS006109
www.fairchildsemi.com
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