Philips Semiconductors
Bus buffer/line driver; 3-state
Product specification
74AHC1G126; 74AHCT1G126
FEATURES
• Symmetrical output impedance
• High noise immunity
• ESD protection:
– HBM EIA/JESD22-A114-A exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V
– CDM EIA/JESD22-C101 exceeds 1000 V.
• Low power dissipation
• Balanced propagation delays
• Very small 5-pin package
• Output capability: standard
• Specified from −40 to +125 °C.
DESCRIPTION
The 74AHC1G/AHCT1G126 is a high-speed Si-gate
CMOS device.
The 74AHC1G/AHCT1G126 provides one non-inverting
buffer/line driver with 3-state output. The 3-state output is
controlled by the output enable input pin (OE). A LOW at
pin OE causes the output to assume a high-impedance
OFF-state.
QUICK REFERENCE DATA
Ground = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
AHC1G AHCT1G
UNIT
tPHL/tPLH propagation delay A to Y
CL = 15 pF; VCC = 5 V
3.4
3.4
ns
CI
input capacitance
1.5
1.5
pF
CPD
power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 9
11
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
2002 Jun 06
2