Philips Semiconductors
Single D-type flip-flop; positive-edge trigger
AC WAVEFORMS
handbook, full pagewidth
VI
D INPUT
GND
VI
CP INPUT
GND
VOH
Q OUTPUT
VOL
VM
tPHL
VM
VM
tPLH
VM
MNA443
Product specification
74AHC1G79;
74AHCT1G79
FAMILY
AHC1G
AHCT1G
VI INPUT
VM
VM
REQUIREMENTS INPUT OUTPUT
GND to VCC
GND to 3.0 V
50% VCC 50% VCC
1.5 V
50% VCC
Fig.5 The clock pulse (CP) to output (Q) propagation delays.
handbook, halfpage
VI
PULSE
GENERATOR
VCC
VO
D.U.T.
RT
CL
MNA101
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance (see Chapter “AC characteristics”).
RT = termination resistance should be equal to the output impedance Z0 of the pulse generator.
Fig.6 Load circuitry for switching times.
1999 May 18
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