74ACTQ16374MTD_Q View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
Manufacturer
74ACTQ16374MTD_Q Datasheet PDF : 8 Pages
| |||
Extended AC Electrical Characteristics
TA 40qC to 85qC
CL 50 pF
TA 40qC to 85qC
Symbol
Parameter
16 Outputs Switching
CL 250 pF
Units
(Note 10)
(Note 11)
Min
Typ
Max
Min
Max
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tOSHL
(Note 12)
Propagation Delay
Data to Output
Output Enable Time
Output Disable Time
Pin to Pin Skew
HL Data to Output
4.7
13.3
6.6
16.3
ns
4.6
11.4
6.4
15.5
3.5
10.4
(Note 13)
ns
3.8
10.9
3.4
8.5
(Note 14)
ns
3.1
8.1
1.3
ns
tOSLH
(Note 12)
Pin to Pin Skew
LH Data to Output
2.1
ns
tOST
(Note 12)
Pin to Pin Skew
LH/HL Data to Output
4.0
ns
Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 12: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (tOST).
Note 13: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 14: The Output Disable Time is dominated by the RC network (500:, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
Units
Conditions
4.5
pF
VCC 5.0V
30
pF
VCC 5.0V
5
www.fairchildsemi.com
|
|
Share Link: 