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74ACT374TTR View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
74ACT374TTR Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
74ACT374
OCTAL D-TYPE FLIP-FLOP
WITH 3 STATE OUTPUTS (NON INVERTED)
s HIGH SPEED:
fMAX = 260MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4µA(MAX.) at TA=25°C
s COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), VIL = 0.8V (MAX.)
s 50TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT374 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP-FLOP with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
These 8 bit D-Type Flip-Flop are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to the logic that were setup at
the D inputs.
While the (OE) input is low, the 8 outputs will be in
PIN CONNECTION AND IEC LOGIC SYMBOLS
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74ACT374B
74ACT374M
T&R
74ACT374MTR
74ACT374TTR
a normal logic state (high or low logic level); when
the OE is high the outputs go to the high
impedance state.
The output control does not affect the internal
operation of flip-flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
April 2001
1/11
 

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